Data is digitally stored in semiconductor memory devices. These semiconductor memory devices fall into one of two categories. Volatile memory devices retain their data only when they are powered on; whereas, non-volatile memory chips can retain the data even if no external power is being supplied to the memory device. One popular form of non-volatile memory device is flash memory. Flash memory is versatile because it can be erased and programmed multiple times. Furthermore, flash memory is relatively inexpensive compared to other types of non-volatile memory devices. Consequently, flash memory is ideal for applications that demand significant amounts of non-volatile, solid-state storage. Examples of applications employing flash memory include USB flash drives, digital audio players, digital cameras and camcorders, mobile phones, automotive control systems, gaming consoles, etc.
Flash memory is typically made up of an array of floating gate transistors, commonly referred to as memory “cells.” One or more bits of data are stored as charge by each memory cell. For example, dual bit memory devices use a silicon-oxide-nitride-oxide-silicon (SONOS) type architecture in which a lower layer of silicon oxide is formed over a semiconductor substrate that is typically silicon. A layer of silicon nitride is formed on the lower layer of silicon oxide, an upper layer of silicon oxide is formed on the layer of silicon nitride and a layer of an electrically conductive material is formed on the upper layer of silicon oxide. The combination of the lower silicon oxide layer, the silicon nitride layer, and the upper silicon oxide layer are capable of trapping charge and are commonly referred to as a charge trapping dielectric structure or layer. It should be noted that the charge trapping structure is defined as a stack of ONO. When more than one bit of information is stored in the charge trapping structure, the memory device is referred to as a dual bit memory device. Bit lines are typically formed in the portion of the semiconductor substrate that is below the charge trapping structure and word lines may be formed from the layer of electrically conductive material that is disposed on the charge trapping structure. This arrangement enables flash memory cells to be manufactured efficiently and economically.
Various semiconductor fabrication processes use masks to help align the memory cells. Aligning the cells produces a more organized and compact design. Although masking techniques properly align the cells, scaling becomes an issue. It becomes harder to place the cells closer together. It is important to place the cells as close together without impacting their functionality because denser cells can hold more data for a given semiconductor area. In other words, tighter tolerances allow for greater memory capacity at reduced cost.
A self-aligned process has been developed to help alleviate the scaling issues associated with the use of masks. The self-aligned process eliminates the need to use masks for alignment purposes. FIG. 1 shows a cross-sectional view of an exemplary self-aligned memory device. It can be seen that each active region 101-103 is separated on each side by STI trenches 104-107. The trenches are fanned through a shallow trench isolation (STI) process. Any number or combination of layers can be deposited or grown over the active regions 101-103. For example, a tunnel oxide layer (optional), ONO (ONO stands for tunnel oxide-nitride-top oxide) stacks 108-110, polysilicon layer(s) 111, etc. can be formed over the active regions 101-103. Notice that the wings formed as part of the ONO stacks 108-110 bend upwards and extend outwards to the STI trenches 104-107. This limits how closely the memory cells can be placed together. In other words, this limits the scalability of memory devices using such a self-aligned fabrication process.